Completed Supervised Theses:

A New Fault-Tolerant Real-Time Ethernet Protocol: Design and Evaluation

Emre Atik, M.S. Thesis, Defense date:  January 2021, Co-advised with Prof. Dr. Klaus Werner Schmidt  

 

Abstract:

This thesis is motivated by the communication requirements of contemporary realtime and embedded applications. These requirements are high-bandwidth, fault tolerance, determinism that allows schedulability and bounded latency, broadcast capability, accommodating sporadic traffic efficiently together with periodic traffic, and finally low cost, COTS interface hardware. To this end, we propose a novel protocol, Shared Queue based Dynamic Slot Reservation (SQDSR) complete with message format, medium access and fault tolerance mechanisms. SQDSR implements a time-slotted synchronized communication layer over shared medium 100 Mbps Ethernet. SQDSR exploits the shared medium for broadcast capability, distributed scheduling of messages and fault tolerance. Furthermore, no switches are required that reduce the cost of implementation. The performance of SQDSR is evaluated with OMNeT++ simulator with a realistic message set and node topology from an avionics application. To this end, we compare the performance of SQDSR to AFDX (Avionics Full-Duplex Switched Ethernet) which is a widely used Ethernet-based communication protocol. The evaluationresults show that SQDSR fulfills the requirements of the contemporary real-time embedded applications.

Thesis overview  


Dynamic Resource Allocation in Virtualized Networks for Network Slicing

Ceren Canpolat, M.S. Thesis, Defense date:  February 2020 

 

Abstract:

The developments of 5G wireless technology, enables serving to various vertical industries through sharing a common infrastructure. To this end, multi-tenancy support of these diverse industries are realized on virtualized networks with the help of network slicing. The introduction of sharing brings many challenges such as QoS satisfaction, fairness and performance isolation among slices. The diversity of these slices mainly lies in their data rate requests and user populations. The slices with high data rate traffic requests are often given large number of resources. That resource allocation approach leaves the slice requests for low data rate slices out of the network. Overcoming all of these challenges with an efficient resource allocation approach is the main concern of this work. In this thesis, we propose DUCA (Dynamic User Count Aware) network slicing,a novel resource allocation scheme for virtualized radio access networks (RAN). DUCA’s resource allocation objective is to serve large number of user requests with high resource utilization results in the presence of diverse slice requirements. To this end, DUCA is formulated with an additional user count parameter so that not only requested amount of data rates but also user populations of slices can effect resource allocation. DUCA is compared with other resource allocation schemes under different network configurations. Simulation results show that the proposed DUCA outperforms compared resource allocation methods.
 

Thesis overview  


Clock Synchronization Algorithms on a Software Defined CAN Controller: Implementation and Evaluation

Serkan Yalçın, M.S. Thesis, Defense date:  September 2019, Co-advised with Prof. Dr. Klaus Werner Schmidt 

Abstract:

Many advanced driver-assistance systems (ADAS) and in-vehicle applications require coordination for their safety-critical tasks. To achieve such a coordination, different electronic control units (ECUs) in the system should synchronize their clocks in order to share a global time. Although the controller area network (CAN) is the most widely used communication bus for the information exchange among ECUs, it does not support the required clock synchronization. Moreover, even several advanced clock synchronization methods for CAN have been suggested in the literature, they require modifications of the CAN driver, which is generally implemented in hardware and not accessible to modifications. The first aim of this thesis is the implementation of a software-defined CAN controller (SDCC) which enables modifications to the standard CAN driver. This SDCC is compatible to standard CAN controllers. The second aim of the thesis is the realization of new clock synchronization algorithms for CAN based on the SDCC including modifications to the classical CAN driver. The performance of the new algorithms is evaluated and compared to existing clock synchronization algorithms for CAN.
 


Train Communication Network, Multifunction Vehicle Bus, Scheduling, Integer Linear Programming, Heuristics

Mustafa Çağlar Güldiken, M.S. Thesis, Defense date:  September 2019, Co-advised with Prof. Dr. Klaus Werner Schmidt 

Abstract:

Train communication network comprises different standards such as the Wire Train Bus (WTB) for the data exchange among different vehicles and the Multifunction Vehicle Bus (MVB) for the data communication within vehicles. Specifically, MVB is a highly robust real-time field bus specifically designed for control systems built into rail-vehicles. MVB supports both periodic process data and sporadic message data transfers in the form of telegrams.

In order to achieve timely and efficient data exchange on MVB, the available bandwidth has to be used efficiently. Accordingly, the main focus of this thesis is the development of systematic scheduling approaches for periodic telegrams on MVB. In this respect, the thesis provides four main contributions. First, the thesis proposes an original integer linear programming (ILP) formulation for the schedule computation on MVB. Second, the thesis develops 5 basic heuristic algorithms for the fast computation of feasible MVB schedules. Third, the thesis introduces several swap operations for improving the schedules obtained from the basic heuristics. Finally, the thesis presents a comprehensive evaluation of the developed scheduling methods. This evaluation shows that, different from the proposed heuristics, the ILP formulation cannot provide solution schedules for large telegram sets with reasonable run-times. Specifically, two of the proposed heuristics and two of the developed swap operations are found most suitable as a practical solution to the MVB scheduling problem.


Generalized Resource Management for Heterogeneous Cloud Data Centers

Ahmet Erol, M.S. Thesis, Defense date:  September 2019 

 

Abstract:

OpenStack is a widely used management tool for cloud computing which is designed to work on servers and allocate standard computing resources such as CPU, memory or disk. The current trend for integrating different hardware accelerators such as FPGAs and GPUs in the cloud requires managing these heterogeneous resources. In this thesis, we propose a generalization for OpenStack Nova project which extends the relevant data structures to include these new resources. More importantly, we present a new lightweight Nova Compute module that we call Nova-G Compute. Nova-G Compute is suitable to work with different hardware platforms and can communicate with the rest of the OpenStack Projects. We implement a hypervisor-like software to enable Nova-G Compute accessing the FPGA resources. We perform experimental evaluation of Nova-G Compute using the known and used OpenStack benchmarking tool Rally. Our results show that Nova-G Compute works as desired without any reduced performance compared to standard Nova.
 

Thesis overview  

 

 


Optimal Dynamic Resource Allocation for Heterogenous Cloud Data Centers

Nazım Umut Ekici, M.S. Thesis, Defense date:  September 2019, Co-advised with Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

Today's data centers are mostly cloud-based with virtualized servers to provide on-demand scalability and flexibility of the available resources such as CPU, memory, data storage and network bandwidth. Heterogeneous cloud data centers (CDCs) offer hardware accelerators in addition to these standard cloud server resources. A cloud data center provider may provide Infrastructure as a Service and Platform as a Service (IPaaS), where the user gets a virtual machine (VM) with processing, memory, storage and networking resources, which can be installed with any desired operating system and software. Differently, Software as a Service (SaaS), only enables user access to provided application for example via a web browser without any control of the underlying infrastructure.

In this context, it is important to note that the data processing for SaaS can be executed on different physical resources such as a server as well as a hardware accelerator with different performance and power consumption. To this end, a very significant feature of heterogeneous CDCs is that they offer the flexibility of meeting user demands for SaaS by choosing among the available physical resource alternatives. To utilize this flexibility, a CDC resource manager must decide which resource alternative will be chosen, along with the decision of the physical resource the request will be assigned to.

In this thesis we propose ACCLOUD-MAN (ACCelerated CLOUD MANager), a novel resource manager for heterogeneous CDCs. ACCLOUD-MAN’s resource management objective is to reduce the power consumption of the CDC in order to support green computing. To this end, the resource allocation problem is modeled as an integer linear programming problem and is implemented in MATLAB, along with a cloud data center simulation platform. We evaluate the performance of ACCLOUD-MAN under different realistic cloud workloads. Simulation results show that the proposed ACCLOUD-MAN outperforms existing resource allocation methods such as OpenStack.
 

Thesis overview  

 

 


A Link Delay Computation Method for the Quality of Service Support in Software Defined Networks

Efe Balo, M.S. Thesis, Defense date:  September 2019 

 

Abstract:

Packet switched networks cannot provide tight delay bounds that are required by certain types of applications despite facilitating high throughput. Therefore, delay measurementtechniquesforpacket-switchednetworkshavealwaysgrabbedtheattention of the community to both utilize advantages of packet-switched networks and provide a realistic end to end delay prediction of packets. Software De?ned Networking (SDN) isa new paradigmofpacket-switchednetworkingwhichgathersmanagement functionality of network in a logically single controller. SDN is thought to eliminate problems of legacy layered architecture by utilizing the control information coming from all network layers. However, in SDN topology, control plane and data plane are separated which implies control packets for network management ?ow in a different channel than datapath channel. Moreover, the SDN controller has to have a decision metric similar to legacy link-state computation approaches in order to calculate the most ef?cient route in the topology. All of these indicate that link delay computation in SDN needs new perspectives different than the legacy network to achieve its proper operation. In this thesis, we propose a link delay computation method for SDN topologies. For this purpose, we construct a framework which uses standard OpenFlow messages and computes the switch queuing delay in run-time. In this framework, we model each queue in SDN switches as a G/G/1 queue and measure the ingress traf?c with OpenFlow meters. Then, we utilize meter statistics to obtain mean and variance of interarrival times between packets. After ?nding the average state of the queues we eventually infer the respective queuing delay from Little’s equation. We demonstrate our method in three cases which are single ?ow per queue, multiple ?ows per queue and a test application which uses our delay information to determine the fastest queue of an SDN switch port. Also, we discuss the accuracy and the application limitations of the proposed method.
 

Thesis overview  

 

 


C³: Configurable CAN FD Controller: Design, Implementation and Evaluation

Mehmet Ertuğ Afşin, M.S. Thesis, Defense date:  February 2018, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

CAN FD (Controller Area Network with Flexible Data Rate) is a new communication standard, compatible with CAN. Different from CAN, CAN FD switches to high data rate during data transmission and allows payloads up to 64 bytes. In this thesis, we propose C3: Configurable CAN FD Controller which features up to fully configurable 96 TX and 96 RX buffers organized as mailboxes. Each RX buffer has dedicated acceptance filters. The host MCU sees C3 as a memory mapped device and interfaces with it via SPI protocol which is designed and developed in the scope of this thesis. Different from existing CAN FD Controllers, C3 provides run time configurable number of buffers and individual buffer sizes which makes it best use of a single hardware for every application. Furthermore, it provides efficient and flexible usage of a limited embedded memory. C3 is implemented on a Xilinx Virtex 5 FPGA demo board as an IP Core and its functions are verified at 2Mbps and the response time measurements are performed to evaluate the timing performance.
 

Thesis overview  Demo video

 


Controller Area Network with Offset Scheduling: Improved Offset Assignment Algorithms And Computation Of Response Time Distributions

Ahmet Batur, M.S. Thesis, Defense date: February 2018, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

The Controller Area Network (CAN) is the most widely-used in-vehicle communication bus in the automotive industry. CAN enables the exchange of data among different electronic control units (ECUs) of a vehicle via messages. The basic requirement for the design of CAN is to guarantee that the worst-case response time (WCRT) of each message is smaller than its specified deadline. Hereby, it is generally desired to achieve small WCRTs that leave sufficient slack to the message deadline. In addition, it has to be noted that it might be very unlikely that a message experiences the WCRT when being transmitted on CAN. That is, instead of only considering the message WCRT for the design of CAN, it is beneficial to determine the actual response-time distribution of each message, which indicates the probability of experiencing a certain response time. In order to achieve small WCRTs, the idea of offset scheduling has been introduced. In this setting, messages on CAN are released with offsets in order to avoid message bursts that lead to undesirably large response times. In order to use offset scheduling efficiently, it is required to assign a suitable offset to each message. To this end, a load distribution (LD) algorithm is proposed in the existing literature. The first contribution of this thesis is the development of new algorithms for the offset assignment on CAN. Evaluating different example scenarios, the thesis shows that the proposed algorithms outperform the existing LD algorithm in most of the cases. As the second contribution, the thesis studies the computation of response time distributions. First, an algorithm for determining the exact response-time distribution of each message on CAN is proposed. Since this algorithm comes with a high computational complexity, it cannot be applied if there are too many messages on a CAN bus. Moreover, experimental results show that the response time distribution depends mostly on the initial phasing of the nodes. Therefore exact response time distribution as computed is not observed in the measurements. In response to this observation, the thesis proposes the computation of a local response time distribution and develops and implements a weak synchronization method which bounds the phase shift between the nodes. The resulting computed local response time distribution shows a very tight match with measured response time distributions.
 

Thesis overview  

 


An End-To-End Communication Architecture for Intelligent Transportation Systems: Design, Implementation and Latency Analysis

Çağatay Bağcı, M.S. Thesis, Defense date:  February 2018

 

Abstract:

Vehicle to anything (V2X) communication is a very significant component of Intelligent Transport Systems (ITS) applications. This thesis proposes an application layer communication architecture, ITSVeCon for V2X communications which enables communication among the end-hosts which can be vehicle Electronic Control Units (ECU)’s, Road Side Units (RSU)s, computers, smart phones or third party service providers. All these end-hosts are bi-directionally connected to the ITSVeCon Server where this server carries out application layer switching realizing unicast or multicast communication. The architecture consists of a layered software and network protocol stack with message formats and rules, which are implemented in the end-hosts and the ITSVeCon server. To this end, this thesis presents the ITSVeCon realization on the vehicle On Board Unit (OBU) and the ITSVeCon server. The OBU realization further fulfills the gateway functionality between the in-vehicle CAN network and the Internet. The ITSVeCon implementation features WebSockets carrying messages in JSON format, Publish and Subscribe pattern and NTP synchronization to enable V2X communications for real time ITS applications. To this end, the proposed architecture allows the seamless running on different ITS applications on different types of host devices. This thesis proposes the cellular communications as the wireless communication technology for the vehicle. To this end, the end-to-end communication path in ITSVeCon consists of cellular access and IP core network over multiple nodes and network segments. A very important contribution of the thesis is the measurement set-up, detailed experiment scenarios and measurement results of the end-to-end delay components. The measured end to end delay values are close to 100 ms with embedded component delays under 4 ms and large cellular network access delay under 3G network. Hence, a complementary short range wireless interface is proposed in this thesis as the second option to improve communication and functional tests of this option is carried out. With the improvements in technology, around 10 ms end to end delay value can be achieved with 4G and 1 ms end to end delay value is expected to be accomplished with 5G. .
 

Thesis overview  Demo video

 


Efficient and Fair Adaptive Streaming: Algorithm, Implementation and Evaluation

Ahmet Öge, M.S. Thesis, Defense date: June 2017

 

Abstract:

HTTP Adaptive Streaming (HAS) is a popular video streaming method where the client downloads video segments over standard HTTP protocol. In HAS, the server stores the video segments that are encoded in different qualities which determine the video bit rates. To this end, the client first downloads a file which describes the video segments. Then, using a rate adaptation algorithm, the client decides on the most appropriate video bit rate for the next segment to download and sends an HTTP request for that segment. The rate adaptation algorithm utilizes measurements of the network bandwidth by dividing the previously downloaded segments' sizes by their download times. HAS exploits that HTTP is an ubiquitous application layer protocol which can easily pass any network device, firewall and Network Address Translation.

Video streaming performance is measured by the user's perception that is quantified by Quality of Experience (QoE). Accordingly, video freezes must be avoided as they decrease QoE significantly. The client aims for downloading at the highest quality utilizing the available bandwidth as much as possible. However, if the requested bit rate is increased too much, delays and packet loss events drive the client to decrease the bit rate subsequently. Such frequent rate switches decrease the QoE. Furthermore, it is desired that fairness among the clients is preserved where the clients that stream over a common bottleneck link share the bandwidth fairly.

In this thesis, we provide an Efficient and Fair Adaptive STreaming (EFAST) architecture to improve the performance of HAS according to the performance metrics that are defined above. In this architecture, clients rate adaptation is implemented by using a Fuzzy Logic Controller. The inputs of EFAST Fuzzy Logic Controller are the receiver buffer size and the estimated bandwidth. After fuzzy control steps, it selects a proper video bit rate of next segment. An analytical model of rate adaptation algorithm is defined to show that EFAST achieves the desired bit rate and buffer occupancy. We implement EFAST in both simulation environment and in real life network. We then perform experiments that evaluate the performance of EFAST in comprehensive network scenarios. Furthermore, we compare EFAST to other well-known HAS rate adaptation algorithms. Our results show that EFAST has more fairly bandwidth allocation among clients who share bottleneck, low switch rate changes, and high bottleneck efficiency with no buffer depletion.
 

Thesis overview

 


Efficient algorithms for the frame packing and slot allocation of FlexRay v3.0

Cumhur Çakmak, M.S. Thesis, Defense date: February 2017, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

Abstract:

Contemporary vehicles employ a large number of Electronic Control Units (ECUs), sensors and actuators that exchange signals over an in-vehicle network (IVN). These signals are packed in frames which are transmitted according to a precomputed schedule to satisfy the stringent real time requirements of the vehicle operation. Both the signal packing and scheduling algorithms affect the utilization and timing properties of the IVN and hence the entire vehicle electronic system. Despite the offline computation, the run-time of these algorithms might become prohibitively long as the number of signals increases.

This thesis proposes signal packing and scheduling algorithms for the Static Segment of the FlexRay IVN standard which is dedicated to the transmission of periodic signals. The proposed algorithms achieve high bandwidth utilization, fulfill the timing requirements and run in feasible times. To this end, the first contribution of the thesis is an Integer Linear Program (ILP) formulation to pack signals into FlexRay frames based on their period properties. The second contribution is a post-processing algorithm to improve the bandwidth utilization. The third contribution is adapting an existing scheduling algorithm to the new version FlexRay v3.0 to achieve feasible schedules under the developed packing methods. The proposed algorithms are applied to signal sets with different properties to demonstrate their advantages compared to previous work in the literature.

 Thesis overview


A Low Latency, High Throughput and Scalable Hardware Architecture for Flow Tables in Software Defined Networks 

 

Göksan Eral, M.S. Thesis, Defense date: September 2016

 

Abstract:

Software Defined Networking (SDN) is a new paradigm which requires multi-field packet classification for each received packet by looking up Flow Tables which contain a large number of rules and corresponding actions. The rules are defined by upto 15 packet header fields including IP source and destination address. If more than one rule rule matches then the action of the highest priority rule is executed. Furthermore rules with wildcard fields are possible. The SDN Flow Table should scale with the rule count while providing high throughput supporting the Gbps network data rates. In addition, recent data center applications such as high frequency/speed trading require ultra low latency. Motivated by these requirements, this thesis proposes
Fast Scalable SDN Table (FASST), a hardware architecture for a low latency, scalable and high throughput SDN Flow Table Implementation. FASST provides a high throughput up to 200 Mega Packet-Per-Second (MPPS) while achieving a very low average latency. To this end, FASST caches the frequently accessed rules exploiting the known temporal locality in the network traffic. FASST is implemented and evaluated on real hardware using Altera Stratix-V state-of-the-art FPGA. For a netv work characteristics showing strong locality, FASST always achieves a lower average latency compared to recent works with a decrease of up to %97.

Thesis overview 


 

TZAR – Time Zone Based Approximation To Ring: An Autonomous Protection Switching Algorithm  for Globally Resilient Optical Transport Networks

 

Fatih Düzgün, M.S. Thesis, Defense date: February 2016

Abstract:

Widespread deployment of new generation high-speed networks, developments in large capacity DWDM technologies, and continuous demand for increasingly resilient global Internet services necessitates a revision on optical transport networks. Considered to be one of the most promising recent phenomena in that sense, OTN is evolving to become a major core switching platform.In this thesis, we briefly present the progress in optical transport networking from hardware architecture and software hierarchy points of views. Then, trends in protection switching are pointed out through a peculiar taxonomy on computational, topological, and efficiency aspects. Finally, an autonomous, low complexity and inter-disciplinary (incorporating automatic protection switching of optical networks with distance vector routing of mobile ad-hoc networks) lightpath recovery algorithm is offered based on time-zone awareness of OTN nodes to fulfill the basic requirements expected from mesh optical networks. The proposed algorithm is evaluated with simulation in comparison to two well-known algorithms.


 

Dynamic Analysis For Complex Event Processing

 

Muhammet Oğuz Özcan, M.S. Thesis, Defense date: December 2015, Co-advised with Associate Prof. Dr. Ali Doğru

 

Abstract:

Analysis facilities are developed in the course of this thesis for a domain-specific real-time and rule-based language along with a supporting tool. Such analysis facilities are required due to the need for investigating the functional correctness and stringent timing properties expected to take place in the software developed through this language. An early version of this language was developed during a Ph.D. study for the domain of fault management in mission critical systems. Five program analysis facilities are proposed and tested with randomly generated numbers of events and rules. Also, discussions about static and dynamic analysis in the event processing domain are presented along with a comparison of related existing tools. The comparisons of existing tools include the two different implementations of the similar design for interpreters for the language. The different implementations involved the languages C++ and Python.

Thesis overview


Controller Area Network (CAN) Response Time Analysis and Scheduling For Advanced Topics: Offsets, FIFO Queues and Gateways

Burak Alkan, M.S. Thesis, Defense date: February 2015, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

Abstract:

Controller Area Network (CAN) is the most widely used in-vehicle network for the communication among electronic control units (ECUs). CAN has a priority-based arbitration mechanism and the classical usage of CAN assumes the implementation of priority queues (PQs) on ECUs. Based on this assumption, the literature provides efficient algorithms for the computation of worst-case response times (WCRTs) of messages as well as for the appropriate assignment of priorities to messages in order to meet real-time guarantees such as message deadlines.

In contemporary CAN networks there are several extensions to the classical case. First, the addition of new functionality to vehicles requires adding new messages with appropriate priorities to existing CAN networks. Second, FIFO queues (FQs) might be used instead of PQs for easier implementation. Third, due to the ever-increasing bus load, CAN networks are usually divided into several segments that are connected via gateways to decrease the contention among messages. Fourth, a further measure is to distribute the message transmission of each ECU over time by assigning transmission offsets to messages. All of the stated extensions require new methods for WCRT analysis and priority assignment on CAN.

This thesis has a list of contributions that address the extensions for CAN as listed above. Regarding offset scheduling; different schedulability analysis methods for message sets with given offset and priority assignments are incorporated to a previous offset assignment algorithm. Then, a new algorithm which simultaneously assigns the message offsets and priorities is proposed. Regarding ECUs with FIFO queues; the previous schedulability analysis is improved to decrease its run time and then this analysis is used in an algorithm that assigns the priorities to the new messages that extend an existing CAN network. Regarding gateways; an algorithmic priority assignment is proposed for ECUs with priority queues and the schedulability analysis for CAN networks with gateways is extended to FIFO queues.

All of the algorithms that are used and developed in this thesis are implemented in C++ to integrate into a novel in-vehicle network analysis and design tool; AUTONET.

Thesis overview


A Frame Packing Method to Improve the Schedulability on CAN and CAN-FD

Gökhan Urul, M.S. Thesis, Defense date: February 2015, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

Abstract:

Controller Area Network(CAN) is the most widely used network in vehicles. Today systems can fill a CAN network's communication bandwidth to its limit. There two main constraints while constructing set of frames to use vehicle network more efficient; minimizing bandwidth consumption and keeping network schedulable which conclude a NP-hard problem on frame packing. The aim of this study is to explore the existing literature on frame packing problem and to solve the problem of generating a schedulable frame set which minimizes the bandwidth utilization on CAN and CAN-FD network. As a part of the solution, we propose an heuristic that solves the optimization problem for signals in CAN and also CAN-FD. The results of our systematically conducted experiments show that, our heuristic provides more effective results than existing techniques.

Thesis overview


A generic and Extendable System Architecture for Intelligent Transportation Systems

Kaan Çetinkaya, M.S. Thesis, Defense date: January 2015

Abstract:

Intelligent Transportation Systems (ITS) are distributed systems with different communicating parties which are vehicles with ITS-supporting On Board Units (OBUs), Road Side Units (RSU) and user mobile devices. These parties collectively run application services that are developed and managed by different application service providers by communicating among each other under certain timing constraints. In the current state of art, hardware, software and communications that are required to implement a given ITS application are all specifically re-designed for each application service. This thesis presents a system architecture named as Car Content Delivery (CarCoDe) for ITS application development complete with a software stack and communication specifications. CarCoDe is generic and can be used by all ITS parties by defining the relevant specific features. It provides a simple software stack and supports both short range and long range communications over a third node. Furthermore, CarCoDe has been attached with great importance to flexibility and modularity features which make it extendable for future contributions. The features of CarCode are demonstrated by a realization of it for a vehicle OBU and implementing an icy road warning application.

Thesis overview  Project Leaflet


UNIBUS: A Universal Hardware Architecture For Serial Bus Interfaces With Real-Time Support

 

Mehdi Duman, M.S. Thesis, Defense date: January 2015

 

Abstract:

Serial bus communication is widely used in different application areas such as Ethernet in computer networking, CAN bus in in-vehicle communications, MIL-STD 1553B in military avionics and UART for peripheral device communication. This thesis work presents UNIBUS (Universal Bus); an abstract, generic block level hardware architecture for implementing serial bus interfaces. UNIBUS realizes the physical and data link layer functions supporting the strict timing requirements for bit operations and synchronization.

The hardware blocks and signal interfaces among these blocks are designed to separate the protocol specific and protocol independent components to increase reusability. A specific serial bus protocol can be implemented using UNIBUS by defining the protocol specific operations and interfaces.

The versatility of UNIBUS is demonstrated by realizing CAN, UART, ARINC-708, ARINC-717 and MIL-STD-1553B on this architecture. These serial bus interfaces are purposely selected to be from different application areas and levels of complexity. All these interfaces are implemented using MODELSIM simulation tool and tested by realizing a sender and receiver that exchange messages as specified. Furthermore MIL-STD- 1553B is fully implemented on FPGA and its correctness is verified by communication to a commercial chip. The analysis of the resource and power consumption of the realizations shows that the generality of the architecture does not decrease the efficiency of the implementations.

UNIBUS decreases the hardware development time for existing and possibly new serial bus protocols by providing the readiliy designed blocks and signal interfaces. Furthermore UNIBUS increases the reliability of the design as the reused protocol independent components that are common among different protocols need to be verified only once and the blocks together with their interfaces are clearly defined. UNIBUS can be both used for the development of full scale serial bus interface components to be used in real systems as well as developing test benches for existing products. In such deployment, a given bus interface's desired functions can be implemented on UNIBUS to achieve a communicating counterpart for the tested component.

Thesis overview Demo video


Software Implementations of QoS Scheduling Algorithms for High Speed Networks 

 

Aydın Pehlivanlı, M.S. Thesis, Defense date: January 2015

 

Abstract:

The end to end Quality of Service (QoS) support for the dominating multimedia traffic in the contemporary computer networks is achieved by implementing schedulers in the routers and deploying traffic shapers. To this end, realistic modeling and simulation of these components is essential for network performance evaluation.
The first contribution of this thesis is the design and implementation of a C++ simulator QueST (Quality of Service simulaTor) for this task. QueST is a modular cycle accurate simulator with a detailed modeling of the traffic flows, shapers and schedulers. The traffic generators and the schedulers of QueST are verified by comparison to the respective analytical models.
The QoS schedulers are data plane components in routers which have to operate at 10s of Gbps rates. Hence, the increasing scheduling complexity with the number of flows is an important problem. This problem can be alleviated by reducing the number of flows by traffic aggregation.
The second contribution of this thesis is the evaluation of previously developed Window Based Fair Aggregator (WBFA) in QueST under a large number of case studies to investigate its features and benefits as well as optimal parameter selection.

Thesis overview


 

Implementation and Performance Analysis Of Switch Fabric Schedulers With a New Accurate Simulator Software

 

Ahmet Ada, M.S. Thesis, Defense date: September 2014

 

Abstract:

The switches and routers in computer networks forward the incoming  packets that arrive at input ports to their output ports where the connections between input lines and output lines are made by a switch  fabric. If the fabric speed can match the aggregate capacity of all input ports, the queuing of the packets is at the output ports. Such output queued arrangements yield the best throughput and delay for the packets together with different levels of Quality of Service Support (QoS) to different flows. However, the speed limits for these fabrics result in queuing at the input ports in practical switch/router implementations.  Such devices require the scheduling of the switch fabric which is the decision of the matched input output port pairs. To this end, the design of these fabric schedulers for achieving high throughput, low delay as well as QoS support is an important research problem.  The first contribution of this the- sis is a software simulator  that is called SwitchSim that accurately simulates switch fabric schedulers. The design of the simulator is modular with well defined interfaces following an Object Oriented Approach to enable integrating different scheduler algorithms and traffic generation patterns.  It is important to note that SwitchSim is verified by comparing its results to a hardware scheduler together with to the results of the legacy ISLIP scheduler.  The second contribution  of the thesis is extending ISLIP to support different priority flow to support QoS. Experiments are carried out using SwitchSim to evaluate the proposed fabric schedulers with QoS support and their results are presented with discussions. The results show that up to loads of 70% the proposed algorithms  can provide less  delay to the high priority flows without starving the low priority flows.

Thesis overview


Switch Fabric Schedulers with Intelligent Multi-Class Support: Design, Implementation and Evaluation on FPGA

 

Murat Akpınar, M.S. Thesis, Defense date: September 2014

 

Abstract:

The applications in the contemporary computer networks require end-to-end Quality of Service (QoS). Moreover, di erent applications have di erent QoS requirements. Thus, it is important to support QoS in the network layer routers which can be achieved by scheduling the output queues in output queued routers. However, pure output queued routers are not easy to build. Hence, it is important to equip the fabric schedulers of input queued switches with QoS support. Thus, it is an important research problem to support QoS in input queued routers. In this thesis we investigate the VOQ fabric scheduler algorithms. Better QoS support for di erent applications is possible by implementing per flow queues at the input ports rather than coarse virtual output queues per output port. The first contribution of this thesis is an intelligent multi-class (IMC) VOQ architecture which is independent from fabric scheduler algorithms. Additionally, 2 di erent algorithms are proposed for intelligent side of the IMC VOQ architecture. The second contribution is a modular hardware design for fabric schedulers that support multi class. The design is carried out on FPGA by implementing the well-known ISLIP together with the proposed IMC unit. The correctness of the operation of the designed hardware is verified by comparing to a software simulator. The thesis further presents discussions of implementing other scheduler algorithms using the same hardware architecture and its scalability. The thesis presents the evaluation of FPGA resource usage of proposed IMC VOQ iSLIP.

Thesis overview


 

 

Fast, Efficient and Dynamically Optimized Data and Hardware Architectures for String Matching

 

Salih Zengin, Ph.D. Thesis, Defense date: September 2014, Co-advised with Prof. Dr. Hasan Guran

 

 

Abstract:

Many fields of computing such as network intrusion detection employ string matching modules (SMM) that search for a given set of strings in their input. An SMM is expected to produce correct outcomes while scanning the input data at high rates. Furthermore, the string sets that are searched for are usually large and their sizes increase steadily.

In this thesis, motivated by the requirement of designing fast, accurate and efficient SMMs; we propose a number of SMM architectures that employ Bloom Filters to compactly represent the large amounts of data for the string sets. The proposed architectures address the well-known slowdown problem of the Bloom Filters because of the verifications of the positive matches.

To this end, the first contribution of the thesis is Double Bloom Filter SMM (DBF-SMM) which employs a second Bloom Filter which acts as a verification engine. We present an analysis, evaluation and implementation of the DBF-SMM. We further verify the required functionality of the DBF-SMM by modeling and testing the architecture in SystemC environment. Our analytical and implementation results demonstrate that DBF-SMM is superior with respect to the existing SMMs in terms of response time, string storage efficiency and hardware scalability of the DBF-SMM which demonstrates its superior performance compared to the previous Bloom Filter based SMM designs. Our analytical and implementation results demonstrate that DBF-SMM is superior with respect to the existing Bloom Filter based SMM designs in terms of response time, string storage efficiency and hardware scalability.
 

 Thesis overview  


 

 

Dependability Design for Distributed Real-Time Systems with Broadcast Communication

 

Yusuf Bora Kartal, Ph.D. Thesis, Defense date: June 2014

 

Abstract:

The operation of distributed systems relies on the timely exchange of message data via dependable communication networks. Previous works suggest hardware redundancy for potential faults in the underlying network infrastructure to achieve dependability. However, software faults and faults that cannot be resolved on the hardware level are not considered in the existing literature. This work proposes a new method for software fault-tolerant communication in distributed real-time systems with communication networks that support time-slotted operation and broadcast transmission.

Our method implements a dependability plane to be integrated to the existing network stack. It processes dependability information that is piggybacked on application message and uses a time synchronized checkpointing/rollback recovery strategy. The proposed dependability plane is modeled in the framework of timed input/output automata (TIOA) to formally prove its correctness and determine tight bounds for fault-recovery times. Model checking tools are employed to verify the timing and dependability properties of real-time systems. To this end, we present an algorithmic approach for converting TIOA models to be used as input of a well-known model checking software tool UPPAL. We apply our dependability plane design and integrate it to a previously developed real-time communications framework. We further verify the TIOA models of the overall protocol stack by employing our algorithmic conversion to UPPAAL.

 

Thesis overview  


 

Diagnosers for discrete event systems: improved realization and examples

 

Bora Eser Kart, M.S. Thesis, Defense date: February 2014, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

Many complex systems in different areas such as manufacturing, telecommunications or transportation can be modeled as Discrete Event Systems (DES). The task of fault detection and isolation is naturally desired for every system that has the possibility of any fault occurrences in it. To this end, a DES machine that can detect every modeled fault after a bounded number of event occurrence called diagnoser is used.

In this thesis, there are two diagnoser realizations corresponding to the notions of event and language diagnosability. The proposed diagnosers function as centralized diagnosers that run parallel to the given systems and perform online diagnosis. Differing from similar studies, we denote our diagnosers as improved diagnosers because they explicitly give a notification as soon as a faulty behavior is detected. This makes our diagnosers more useful in practice. In addition, our study simplifies the computation of the worst-case delay until a fault is detected. Moreover, we further enhance our improved diagnoser by applying an algorithm to remove unnecessary observations. As a result, fewer sensors are needed and the constructed diagnosers have a smaller size. The merits of the proposed diagnoser approach and the applicability of our algorithmic implementation are demonstrated by a communication network system example.

Thesis overview


 

Combined centralized and decentralized fault diagnosis for discrete event systems

 

Ruhi Karav, M.S. Thesis, Defense date: February 2014, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

Discrete Event Systems (DES) are used for modeling systems such as manufacturing systems, telecommunication systems and transportation systems. It is possible to incorporate the fault model in the DES model together with a fault diagnosis approach to evaluate the robustness and the reliability of the system at the design stage. There are centralized or decentralized fault diagnosis approaches in the literature. The centralized fault diagnosis achieves stronger results however it does not scale to reasonably large systems because of its complexity. The decentralized diagnosis is applicable to real-life systems with a cost of possible misses of faults. This thesis proposes a combination of centralized and decentralized fault diagnosis for DES models. To this end, the thesis makes use of the observation that some parts of the faulty DES behavior might be detected by decentralized diagnosis while other parts need a centralized diagnoser. Hence, the overall complexity of the diagnosis is reduced while maintaining the ability to detect all faults. The thesis proposes a systematic diagnosis approach together with the algorithms and practical applications to manufacturing system and communication network examples.

Thesis overview


 

Simulation-Based VoIP Performance Evaluation under Different Traffic and Codec Conditions

 

Berk Ünlü, M.S. Thesis, Defense date: September 2013

 

Abstract:

One of today’s most popular multimedia applications that needs more investigation and optimization is Voice over Internet Protocol (VoIP). Simulation tools are essential to test existing network technologies and develop new ones. They are effectively used for network analysis and solving design and optimization problems. The focus of this thesis is an extensive simulation study to evaluate the achieved Quality of Service (QoS) support by VoIP traffic under different network topologies, traffic profiles, codecs and queuing mechanisms. To this end, firstly we performed a comparative evaluation of network simulators. Accordingly, we selected ns-2 as our simulation tool because of its wide library of network components and traffic types and its open source facilities. Next, we defined a number of different scenarios guided by previous works in the literature. We conducted a set of simulation experiments with ns-2 and evaluated the VoIP performance parameters such as delay, jitter and packet loss ratio under these scenarios.

Thesis overview


An FPGA implementation of two-step trajectory planning for automatic parking

 

Halil Ertuğrul, M.S. Thesis, Defense date: September 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

The main distinguishing feature of different automatic parking technologies is the method that determines a proper collision-free path. Hereby, the length of the path, the number of halts and the computation time for finding such path are the most relevant performance criteria. In this thesis, a two-step trajectory planning algorithm for automatic parking is considered. The algorithm finds a path that meets all kinematic constraints of the car from its initial position, to the target position while requiring a small number of vehicle halts. It first calculates a collision-free path from the initial position to the target position by maximizing the distance from any obstacle. Since this path usually does not respect the kinematic constraints of the vehicle, a second algorithmic step computes a path that is suitable for the vehicle. In both steps, a set of 48 optimal trajectories is used for the path computations and distance evaluations. Since the trajectory planning algorithm requires complex geometric calculations, it a microprocessor is not suitable for practicable computation times. Hence, an FPGA is chosen for the realization of the trajectory planning algorithm on hardware, enabling parallel processing of the trajectory computations. This thesis describes the hardware design for implementing the trajectory planning algorithm on FPGA. The performed analysis both via simulations and implementation on hardware shows that a speedup in the trajectory computation is obtained. Different from other hardware realizations that are restricted to either only parallel parking or vertical parking, our implementation can handle general parking situations. In addition, our implementation increases the driver comfort by reducing the number of vehicle halts.

Thesis overview Demo video


Implementation and evaluation of the dependability plane for the Dynamic Distributed Dependable Real Time Industrial Protocol (D3RIP)

 

Ömer Berat Sezer, M.S. Thesis, Defense date: September 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

Dynamic Distributed Dependable Real Time Ethernet Industrial Protocol (D3RIP) is a real time industrial communication protocol that runs over shared-medium Ethernet with COTS hardware. The protocol consists of an interface layer that enables time slotted communication and a coordination layer that guarantees collision avoidance and timely delivery of real time messages generated by the control application. At the current development stage, these two layers of the protocol are fully implemented and tested. The scope of this thesis is the implementation of a new plane for D3RIP to achieve dependability. To this end, mechanisms of fault detection and roll back recovery are applied. The interface of the dependability plane to the existing interface layer and coordination layer is defined. Finally the dependability plane is implemented and integrated to the existing protocol stack. A number of tests under different fault scenarios are conducted to demonstrate the plane functionality.

 

Thesis overview   Demo video

 


Implementation and evaluation of the Dynamic Distributed Real Time Industrial Protocol (D2RIP)

 

Adem Kaya, M.S. Thesis, Defense date: September 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

The contemporary large-scale and complex industrial control systems such as manufacturing systems, power plants or chemical processes are realized as distributed systems. Since different controller nodes are usually physically distributed, their coordination and information exchange is commonly realized via industrial communication networks (ICNs). In the last decade, there is an ongoing research effort in both academic and industrial fields to employ Ethernet for industrial communications due to its wide acceptance and use in home and office networks. Although the conventional Ethernet technology is low-cost and very high-speed its nondeterministic behavior does not support real-time traffic.

In this thesis we present the design, implementation and evaluation of the novel ICN protocol D²RIP (Dynamic Distributed Real-time Industrial Communication Protocol) that was proposed in previous work. D²RIP is a fully distributed protocol over shared-medium Ethernet with COTS (Commercial Off-The-Shelf) hardware and provides real-time message delivery guarantees, supports non-real-time traffic. As a distinctive feature in comparison to other ICNs over Ethernet that only support static allocation of real-time and non-real-time bandwidth, D²RIP allows for dynamic allocation of the network capacity among the participating nodes by exploiting knowledge about the deterministic system behavior of industrial systems.

Thesis overview   Demo video

 

 


Design and implementation of hardware architectures for high-speed IP address lookup

 

Nizam Ayyıldız, Ph.D. Thesis, Defense date: August 2013, Co-advised with Prof. Dr. Hasan Guran

 

Abstract:

 

IP address lookup modules for backbone routers should store 100Ks of entries, find the longest prefix match (LPM) for each incoming packet at 10s of Gbps line speed and support thousands of lookup table updates each second. It is desired that these updates are non-blocking, that is without disrupting the ongoing lookups. Furthermore, considering the increasing line rates and table sizes, the scalability of the design is very important. The goal of this thesis is developing hardware IP lookup architectures that perform single clock cycle lookups and non-blocking updates that are entirely carried out on hardware. To this end, we propose
a custom TCAM architecture for IP lookup that we call S-DIRECT-Scalable and Dynamically REConfigurable TCAM and a complete IP lookup solution that utilizes different types of memory that we call SHIP-Scalable Highspeed IP lookup. Both S-DIRECT and SHIP feature a modular design that allows seamless scaling to different table sizes. We implement the developed architectures on FPGA with a resource effcient realization and provide the hardware requirements for implementation on other platforms. We demonstrate the viability of our architectures with a full implementation on FPGA that can store contemporary routing tables.

 

Thesis overview  


HTTP Adaptive Streaming architectures for Video on Demand and Live TV Services

 

Yiğit Özcan, M.S. Thesis, Defense date: August 2013

 

Abstract:

HTTP Adaptive Streaming (HAS) has become a popular video streaming solution since it both benefits from the ubiquitous HTTP protocol and firewall and NAT traversal capabilities of TCP. HAS aims to provide high Quality of Experience (QoE) to the clients under limited and varying bandwidth by rate adaptation algorithms which allow the clients to choose the most appropriate video quality. A rate adaptation algorithm should utilize the available bandwidth. Furthermore, the received video bitrates should not deviate from each other leading to an unfair bandwidth use among the clients. It is also desired to minimize the rate switches as they degrade QoE of the clients. In this thesis, we propose two architectures that operate on HAS. The first architecture is FEedback based Adaptive STreaming over HTTP (FEAST). FEAST enables the clients to adapt their rates according to the total number of clients, average video rate and the average bandwidth information provided by the server. These values are computed as moving averages by the server with a small amount of information sent from the clients. The server side computation is simple and not client specific which makes FEAST a scalable solution. The second architecture is Adaptive LIVE Streaming over HTTP (ALIVE) which enables a high number of clients to watch live TV channels over HTTP. ALIVE is based on enabling the clients to download the contents from nearby clients instead of the server whenever it is possible. ALIVE employs SVC which makes it possible to adapt the video bitrates of the clients even when they download from other clients. ALIVE decreases the load of the server and accommodates more clients as we demonstrate with simulations.

Thesis overview


The development and hardware implementation of a dynamically reconfigurable and area optimized Cyclic Redundancy Check architecture

Özcan Yurt, M.S. Thesis, Defense date: August 2013

 

Abstract:

The Cyclic Redundancy Check (CRC) calculation for data communication protocols is implemented by hardware calculators in several systems due to increasing throughput requirements of data communication protocols. Furthermore CRC is employed in many small scale embedded systems with different types of data communication interfaces that are implemented on FPGA. Resource utilization of these systems is frequently a critical parameter with regards to cost. In many cases, limited logic units of an FPGA have to be used very carefully to fit the design into that platform. In this thesis, we present DAROC-Dynamically Reconfigurable and ARea Optimized CRC, which is a run-time reconfigurable and area-minimized CRC calculator. The ability of reconfiguration enables DAROC calculating different CRCs for several standards with a single instance of implementation. DAROC reaches the throughput of 705 Mbps that is sufficient for the target embedded systems with less resource consumption compared to the previous reconfigurable CRC implementations.

Thesis overview Demo video


Software tool development for the automated configuration of FlexRay networks for in-vehicle communication

Can Öztürk, M.S. Thesis, Defense date: January 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt 

 

Abstract:

The increasing use of electronic components in today’s automobiles demands more powerful in-vehicle network communication protocols. FlexRay protocol, which is expected to be the de-facto standard in the near future, is a deterministic, fault tolerant and fast protocol designed for in vehicle communication. The current de-facto in-vehicle communication standard, CAN, and the future in-vehicle communication standard FlexRay will exist together in future cars. Data exchange between these two standards will be performed via Gateway units. The configuration of such interconnected networks require setting a very large number of parameters in a consistent manner. In this thesis a software configuration tool with user interface support for such in-vehicle networks will be developed.

Thesis overview


The development and hardware implementation of a high-speed adaptable packet switch fabric

Erdem Eyüp Akbaba, M.S. Thesis, Defense date: January 2013

 

Abstract:

Routers have to be fast enough to keep pace with increasing traffic data rate because of the increasing need for network bandwidth and processing. The switch fabric component of a router is a combination of hardware and software which moves the incoming packets to the outgoing ports. The access of the input ports to the switch fabric is controlled by a scheduler which affects the overall performance together with the fabric design. In this thesis we investigate two switch fabric and scheduler architectures, the well-known iSlip fabric scheduler and the Byte-Focal switch. We observe that these two architectures have different behaviors under different input traffic load ranges. The novel contribution of this thesis is a combined switch architecture which is composed of these two architectures that are implemented and run in parallel to selectively forward the packets with lower delay to the outputs to achieve an overall lower average delay. The design of the combined switch is carried out on FPGA and simulated. Our results show that the combined architecture has 100% throughput and a lower average delay compared to the Byte-Focal switch and the input-queued switch with iSlip. On the other hand, our combined switch uses more resources in FPGA than individual iSlip and Byte-Focal switch.

Thesis overview


 

A new service architecture for IPTV over Internet

Merve Özkardeş, M.S. Thesis, Defense date: January 2013

 

Abstract:

Multimedia applications over the Internet and Internet Protocol Television (IPTV) gain a lot of attention. IPTV has a number of service requirements such as; high bandwidth, scalability, minimum delay, jitter and channel switch time. IP multicast, IMS (IP Multimedia System) Protocol and peer-to-peer approaches are proposed for implementing IPTV. However, IP multicast requires all the routers in the core network to possess multicast capability, IMS does not easily scale and P2P cannot efficiently utilize the network resources because of its  completely distributed nature. To this end, we propose new application layer multicast protocol Cluster Based Application Layer Multicast IPTV (CALMTV) which combines application layer multicast, scalable video coding and probing techniques to meet IPTV requirements. We present the components and their relevant algorithms and evaluate the performance of CALMTV with ns2 simulations. Our results compared with the published results of other IPTV architectures show that CALMTV has better performance in end-to-end delay and zapping time.

Thesis overview


 

A software tool for vehicle calibration, diagnosis and test via controller area network

 

Utku Civelek, M.S. Thesis, Defense date: September 2012

 

Abstract:

 

Controller Area Networks (CAN’s) in vehicles need highly sophisticated software tools to be designed and tested in development and production phases. These tools consume a lot of computer resources and usually have complex user interfaces. Therefore, they are not feasible for vehicle service stations where low-performance computers are used and the workers not very familiar with software are employed. In this thesis, we develop a measurement, calibration, test and diagnosis program -diaCAN- that is suitable for service stations. diaCAN can transmit and receive messages over 3 CAN bus channels. It can display and plot the data received from the bus, import network message and Electronic Control Unit (ECU) configurations, and record bus traffic with standard file formats. Moreover, diaCAN can calibrate ECU values, acquire fault records and test vehicle components with CAN Calibration Protocol functions. All of these capabilities are verified and evaluated on a test bed with real CAN bus and ECUs.

Thesis overview


QoC and QoS bargaining for message scheduling in networked control systems

Sinan Şenol, Ph.D. Thesis, Defense date: June 2012, Co-advised with Prof. Dr. Kemal Leblebicioğlu

Abstract:

Networked Control Systems (NCS) are distributed control systems where the sensor signals to the controllers and the control data to the actuators are enclosed in messages and sent over a communication network. On the one hand, the design of an NCS requires ensuring the stability of the control system and achieving system response that is as close as possible to that of an ideal system which demands network resources. On the other hand, these resources are limited and have to be allocated efficiently to accommodate for future system extensions as well as applications other than control purpose. Furthermore the NCS design parameters for the control system messages and the message transmission over the network are interdependent. In this thesis, we propose “Integrated NCS Design (INtERCEDE: Integrated NEtwoRked Control systEm DEsign)” a novel algorithmic approach for the design of NCS which ensures the stability of the control system, brings system response to that of an ideal system as close as desired and conserves network bandwidth at the same time. The core of INtERCEDE is a bargaining game approach which iteratively calculates the message parameters and network service parameters. Our experimental results demonstrate the operation of INtERCEDE and how it computes the optimal design parameters for the example NCS.


 

Development of strategies for reducing the worst-case message response times on the controller area network

 

Vakkas Çelik, M.S. Thesis, Defense date: January 2012, Co-advised with Assistant Prof. Dr. Klaus Werner Schmidt 

Abstract:

The controller area network (CAN) is the de-facto standard for in-vehicle communication. The growth of time-critical applications in modern cars leads to a considerable increase in the message traffic on CAN. Hence, it is essential to determine efficient message schedules on CAN that guarantee that all communicated messages meet their timing constraints. The aim of this thesis is to develop offset scheduling strategies that find feasible schedules for higher bus load levels compared to conventional CAN scheduling approaches. We formulate the offset scheduling as a constraint optimization problem that maximizes the sum of message slacks where slack is defined as the difference between the deadline and the worst-case response time (WCRT) of a message. The constraint to ensure the feasibility of the schedules is keeping all slacks positive. In this respect we propose two heuristic offset scheduling algorithms which integrate an existing method for the WCRT analysis in the schedule computation. We apply our algorithms to various examples and compare the results with a well-known offset scheduling algorithm. The results show that our algorithms can generate feasible schedules at significantly high loads with run times shorter than 5 minutes.


Simulation and performance evaluation of a distributed real-time communication protocol for industrial embedded systems

Güray Aybar, M.S. Thesis, Defense date: December 2011

Abstract:

The Dynamic Distributed Dependable Real-Time Industrial communication Protocol (D3RIP) provides service guarantees for Real-Time traffic and integrates the dynamically changing requirements of automation applications in their operation to efficiently utilize the resources. The protocol dynamically allocates the network resources according to the respective system state. To this end, the protocol architecture consists of an Interface Layer that provides time-slotted operation and a Coordination Layer that assigns each time slot to a unique transmitter device based on a distributed computation.

In this thesis, a software simulator for D3RIP is developed. Using the D3RIP Simulator, modifications in D3RIP can be easily examined without facing complexities in real implementations and extensive effort in terms of time and cost. The simulator simulates the Interface Layer, the Coordination Layer and additionally, the Shared Medium. Hence, using the simulator, the system-protocol couple can be easily analyzed, tested and further improvements on D3RIP can be achieved with the least amount of effort.

The simulator implements the Timed Input Output Automata (TIOA) models of the D3RIP stack components using C++. The resulting code is compiled on GCC (Gnu Compiler Collection). The logs of the simulation runs and the real system with 2 devices connected via cross 100MbE cables are compared. In a 3ms time slot, the simulator and the system incidents differ about 135µs on the average, causing no asynchronousity in their instantaneous operational states. The D3RIP simulator is useful in keeping track of any variable in the D3RIP system automaton at any instant up to 1µs resolution.


Design and implementation of scheduling and switching architectures for high speed networks

Mustafa Sanlı, Ph.D. Thesis, Defense date: October 2011, Co-advised with Prof. Dr. Hasan Güran

Abstract:

Quality of Service (QoS) schedulers are one of the most important components for the end-to-end QoS support in the Internet. The focus of this thesis is the hardware design and implementation of the Packet Fair QoS schedulers, that is scalable for high line speeds and large number of traffic flows.  FPGA is the selected hardware platform.

 

Previous work on the hardware design and implementation of QoS schedulers are mostly algorithm specific. In this thesis we propose a general architecture for the design of the class of Packet Fair Queuing (PFQ) schedulers. Worst Case Fair Weighted Fair Queuing Plus (WF2Q+) is implemented and tested in hardware to demonstrate the proposed architecture and design enhancements.

 

The maximum line speed that PFQ algorithms can operate decreases as the number of scheduled flows increases.  We propose to aggregate the flows to scale our PFQ architecture to high line speeds. To this end, the Window Based Fair Aggregator (WBFA) algorithm for flow aggregation, provides a tunable trade-off between the efficient use of the available bandwidth and the fairness among the constituent flows. [u1] WBFA is also integrated to our hardware PFQ architecture.

 

We measure the QoS support provided by our PFQ architecture and WBFA by conducting hardware experiments on our custom built high speed network testbed which consists of three data processing cards and a backplane. The input traffic is provided by the traffic hardware traffic generator which is designed in the scope of this thesis.


Implementation and evaluation of a synchronous time-slotted medium access protocol for networked industrial embedded systems

Ahmet Korhan Gözcü, M.S. Thesis, Defense date: September 2011

Abstract:

Dynamic Distributed Dependable Real-time Industrial communication Protocol family (D3RIP), has been proposed in the literature considering the periodic or event-based traffic characteristics of the industrial communication networks. D3RIP framework consists of two protocol families: Interface Layer (IL) protocol family, which is responsible for providing the accurate time-division multiple access (TDMA) on top of a shared-medium broadcast channel, and Coordination Layer (CL), which is defined to fulfill the external requirements of IL. In this thesis, the hardware adaptations of the two protocols, Real-time Access Interface Layer (RAIL) and Time-slotted Interface Layer (TSIL), of the IL protocol family, are implemented. Their performance on both personal computers (PC) and development kits (DK) are observed.


Implementing and evaluating the Coordination Layer and time-synchronization of a new protocol for industrial communication networks

Ulaş Turan, M.S. Thesis, Defense date: September 2011

Abstract:

Currently automation components of large-scale industrial systems are realized with distributed controller devices that use local sensor/actuator events and exchange shared events with communication networks. Fast paced improvement of Ethernet provoked its usage in industrial communication networks. The incompatibility of standard Ethernet protocol with the real-time requirements encouraged industry and academic researchers to provide a resolution for this problem. However, the existing solutions in the literature suggest a static bandwidth allocation for each controller device which usually leads to an inefficient bandwidth use.Dynamic Distributed Dependable Real-time Industrial Communication Protocol (D3RIP) family dynamically updates the necessary bandwidth allocation according to the messages generated by the control application. D3RIP is composed of two protocols; interface layer that provides time-slotted access to the shared medium based on an accurate clock synchronization of the distributed controller devices and coordination layer that decides the ownership of real-time slots. In this thesis, coordination layer protocol of D3RIP family and the IEEE 1588 time synchronization protocol is implemented and tested on the real hardware system that resembles a factory plant floor. In the end, we constructed a system that runs an instance of D3RIP family with 3ms time-slots that guarantees 6.6ms latency for the real-time packets of control application. The results proved that our implementation may be used in distributed controller realizations and encouraged us to further improve the timing constraints.


A faster intrusion detection method for high-speed computer networks

Mehmet Cem Tarım, M.S. Thesis, Defense date: May 2011

Abstract:

The malicious intrusions to computer systems result in the loss of money, time and hidden information which require deployment of intrusion detection systems. Existing intrusion detection methods analyze packet payload to search for certain strings and to match them with a rule database which takes a long time in large size packets. Because of buffer limits, packets may be dropped or the system may stop working due to high CPU load. In this thesis, we investigate signature based intrusion detection with signatures that only depend on the packet header information without payload inspection. To this end, we analyze the well-known DARPA 1998 dataset to manually extract such signatures and construct a new rule set to detect the intrusions. We implement our rule set in a popular intrusion detection software tool, Snort. Furthermore we enhance our rule set with the existing rules of Snort which do not depend on payload inspection. We test our rule set on DARPA data set as well as a new data set that we collect using attack generator tools. Our results show around 30% decrease in detection time with a tolerable decrease in the detection rate. We believe that our method can be used as a complementary component to speed up intrusion detection systems.


Ethernet based real time communications for embedded systems

Ozan Yılmaz, M.S. Thesis, Defense date: May 2010

Abstract:

Fast paced improvement of Ethernet technology has also received attention in the industry field like it did in other fields and ways of usage have started to be studied. As it is understood that the standard Ethernet protocols cannot be used due to the unsatisfied real time requirements, industrial and academic researchers have started to develop solutions to overcome this deficiency. In this thesis, the real hardware adaptations of Real Time Ethernet and RTXX protocol algorithms are implemented and their behaviors on the hardware are observed. Each parameter that affects the system’s real time behavior is individually examined and the solution proposals are discussed.


Inter-connected FlexRay and CAN networks for in-vehicle communication: Gateway implementation and end-to-end performance study

Melih Alkan, M.S. Thesis, Defense date: May 2010

Abstract:

The increasing use of electronic components in today’s automobiles demands more powerful in-vehicle network communication protocols. FlexRay protocol, which is expected to be the de-facto standard in the near future, is a deterministic, fault tolerant and fast protocol designed for in vehicle communication. The current de-facto in-vehicle communication standard, CAN, and the future in-vehicle communication standard FlexRay will exist together in future cars. Data exchange between these two standards will be performed via Gateway units. In this thesis, end-to-end performance of a FlexRay-CAN network connected by a Gateway is evaluated as well as Gateway functionality and processing delay. The results of the experiments, which are performed for a realistic message set with various scheduling schemes, are presented and discussed.


Performance evaluation of FlexRay networks for in-vehicle communication

Ali Demirci, M.S. Thesis, Defense date: November 2009

Abstract:

The increasing use of electronic components in today’s automobiles demands more powerful in-vehicle network communication protocols. FlexRay protocol, which is expected be the de-facto standard in the near future, is a deterministic, fault tolerant and fast protocol designed for in vehicle communication. In the near future, safety critical X-by-Wire applications will be available in the automobiles and FlexRay networks can be used to provide communication for the Electronic Control Units (ECUs) that perform related functions of X-by-Wire applications. In this thesis the performance of the FlexRay networks with various communication scenarios is evaluated in a real time environment and the results are presented. Communication scenarios investigate both static and dynamic segment of the FlexRay and allow evaluating the capabilities of the protocol. Several performance metrics such as utilization, static slot allocation, jitter are defined for the evaluation of the results.


A new feedback-based contention avoidance algorithm for optical burst switching networks

Hadi Alper Toku, M.S. Thesis, Defense date: December 2008

Abstract:

In this thesis, a feedback-based contention avoidance technique based on weighted Dijkstra algorithm is proposed to address the contention avoidance problem for Optical Burst Switching networks. Optical Burst Switching (OBS) has been proposed as a promising technique to support high-bandwidth, bursty data traffic in the next-generation optical Internet. Nevertheless, there are still some challenging issues that need to be solved to achieve an effective implementation of OBS. Contention problem occurs when two or more bursts are destined for the same wavelength. To solve this problem, various reactive contention resolution methods have been proposed in the literature. However, many of them are very vulnerable to network load and may suffer severe loss in case of heavy traffic. By proactively controlling the overall traffic, network is able to update itself in case of high congestion and by means of this method; contention avoidance can be achieved efficiently.

The performance analysis of the proposed algorithm is presented through network simulation results provided by OMNET++ simulation environment. The simulation results show that the proposed contention avoidance technique significantly reduces the burst loss probability as compared to networks without any contention avoidance techniques.


Time-triggered controller area network (TTCAN) communication scheduling: a systematic approach

Uğur Keskin, M.S. Thesis, Defense date: August 2008

Abstract:

Time-Triggered Controller Area Network (TTCAN) is a hybrid communication paradigm with combining both time-triggered and event-triggered traffic scheduling. Different from the standard Controller Area Network (CAN), communication in TTCAN is performed according to a pre-computed, fixed (during system run) schedule that is called as TTCAN System Matrix. Thus, communication performance of TTCAN network is directly related to structure of the system matrix, which makes the design of system matrix a crucial process. The study in this thesis consists of the extended work on the development of a systematic approach for system matrix construction. Methods for periodic message scheduling and an approach for aperiodic message scheduling are proposed with the aim of constructing a feasible system matrix, combining three important aspects: message properties, protocol constraints and system performance requirements in terms of designated performance metrics. Also, system matrix design, analyses and performance evaluation are performed on example message sets with the help of two developed software tools.


Connectionless traffic and variable packet size support in high speed network switches: improvements for the delay-limiter switch

Alican Akçasoy, M.S. Thesis, Defense date: June 2008

Abstract:

Quality of Service (QoS) support for real-time traffic is a critical issue in high-speed networks. The previously proposed Delay-Limiter Switch working with the Framed-Deadline Scheduler (FDS) is a combined input-output queuing (CIOQ) packet switch that can provide end-to-end bandwidth and delay guarantees for connection-oriented traffic. The Delay-Limiter Switch works with fixed-size packets. It has a scalable architecture and can provide QoS support for connection-oriented real-time traffic in a low-complexity fashion. The Delay-Limiter Switch serves connectionless traffic by using the remaining resources from the connection-oriented traffic. In this case, efficient management of the residual resources plays an important role on the performance of the connectionless traffic. This thesis work integrates new methods to the Delay-Limiter Switch that can improve the performance of the connectionless traffic while still serving the connection-oriented traffic with the promised QoS guarantees. A new method that makes it possible for the Delay-Limiter Switch to support variable-sized packets is also proposed.


Testing distributed real-time systems with a distributed test approach

Gökhan Öztaş, M.S. Thesis, Defense date: May 2008

Abstract:

Software testing is an important phase the of software development cycle which reveals faults and ensures correctness of the developed software. Distributed realtime systems are mostly safety critical systems for which the correctness and quality of the software is much more significant. However, majority of the current testing techniques have been developed for sequential (non real-time) software and there is a limited amount of research on testing distributed real-time systems. In this thesis, a proposed approach in the academic literature "testing distributed real-time systems using a distributed test architecture" is implemented and compared to existing software testing practices in a software development company on a case study. Evaluation of the results show the benefits of using the considered distributed test approach on distributed real-time systems in terms of software correctness.


A new approach for the scalable intrusion detection in high-speed networks

Ümit Burak Şahin,  M.S. Thesis, Defense date: December 2007

Abstract:

The increasing network throughput challenges the current Intrusion Detection and Prevention Systems to have compatible high performance data processing. As the networks become faster and faster, the emerging requirement is to improve the performance of the Intrusion Detection and Prevention Systems to keep up with the increased network throughput. In high speed networks, it is very difficult for the traditional systems to process all the packets. Since the throughput of Intrusion Detection and Prevention Systems is not improved as fast as the switches’, routers’ throughputs, it is necessary to develop new detection techniques other than traditional techniques. Observing the flow patterns of intrusions in a computer system, we adopt an Intrusion Detection and Prevention System (ID/PS) technique to detect Layer 2-4 attacks. This thesis implements rule based intrusion prevention system using flow patterns gathered from the devices on the network. This work makes it possible to detect and prevent L2-L4 intrusions by using the flow data, logs and network management information without payload inspection, hence decreasing the load on the signature based IDPS and improving its performance in high-speed networks. Our approach is independent of the underlying network structure provided that certain flow level data can be collected. The performance of our approach is demonstrated in a real large scale network.


Scheduling algorithms for wireless CDMA networks

Serkan Ender Hakyemez,  M.S. Thesis, Defense date: December 2007

Abstract:

In recent years the need for multimedia packet data services in wireless networks has grown rapidly. To overcome that need third generation (3G) mobile services have been proposed. The fast growing demands multimedia services in 3G services brought the need for higher capacity. As a result of this, the improvement on throughput, traffic serving performance has become necessary in 3G systems. Code division multiple access (CDMA) technique is one of the most important 3G wireless mobile techniques that has been defined. The scheduling mechanisms used in CDMA plays an important role on the efficiency of the system. The power, rate and capacity parameters are variable and dependent to each other in designing a scheduling mechanism. The schedulers for CDMA decide which user will use the frequency band at which time interval with what power and rate. In this thesis different type of algorithms used in time slotted CDMA are studied and a new algorithm which supports Quality of Service (QoS) is proposed. The performance analysis of this proposed algorithm is done via simulation in comparison to selected CDMA schedulers.


Routing algorithms for on chip networks

Maksat Atagoziyev,  M.S. Thesis, Defense date: December 2007

Abstract:

Network-on-Chip (NoC) is communication infrastructure for future multi-core Systems-on-Chip (SoCs). NoCs are expected to overcome scalability and performance limitations of Point-to-Point (P2P) and bus-based communication systems. The routing algorithm of a given NoC affects the performance of the system measured with respect to metrics such as latency, throughput and load distribution. In this thesis, the popular Orthogonal One Turn (O1TURN) and Dimension Order Routing algorithms (DOR) for 2D-meshes are implemented by computer simulation. Investigating the effect of parameters such as packet, buffer and topology sizes on the performance of the network, it is observed that the center of the network is loaded more than the edges. A new routing algorithm is proposed and evaluated to achieve a more balanced load distribution. The results show that this goal is achieved with a trade off in latency and throughput in DOR and O1TURN.


An evaluation of aspect-oriented programming for embedded real-time systems

Yusuf Bora Kartal,  M.S. Thesis, Defense date: May 2007

Abstract:

In this thesis work, a detailed evaluation of the use of Aspect Oriented Programming for the implementation of crosscutting concerns in embedded real-time systems is presented. The implementations are first tested in terms of software quality attributes. Then a detailed analysis of the two implementations, according to embedded real-time performance metrics has been carried out. Evaluation results show the benefits of Aspect Oriented Programming in embedded real-time systems.


A novel method for  the detection of P2P traffic in the network backbone inspired by intrusion detection systems

Murat Soysal , M.S. Thesis, Defense date: June 2006

Abstract:

The share of peer-to-peer (P2P) protocol in the total network traffic grows day-by-day in the Turkish Academic Network (UlakNet) similar to the other networks in the world. This growth is mostly because of the popularity of the shared content and the great enhancement in the P2P protocol since it first came out with Napster. The shared files are generally both large and copyrighted. Motivated by the problems of UlakNet with the P2P traffic, we propose a novel method for P2P traffic detection in the network backbone in this thesis. Observing the similarity between detecting traffic that belongs to a specific protocol and detecting an intrusion in a computer system, we adopt an Intrusion Detection System (IDS) technique to detect P2P traffic. Our method is a passive detection procedure that uses traffic flows gathered from border routers. Hence, it is scalable and does not have the problems of other approaches that rely on packet payload data or transport layer ports.


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