ARIA: A QoS-Aware On-Chip Packet Switch for Heterogeneous FPGA/SoC Systems
ARIA is a centralized on-chip packet switch for heterogeneous FPGA/SoC systems, combining virtual output queues, an N × N crossbar, packet reassembly, and CAROM, a weighted request–grant–accept arbiter with deterministic priority progression.
The VHDL design, synthesized on an AMD Kintex UltraScale+ FPGA, provides configurable relative service differentiation while preserving weighted service behavior through packet reassembly.