Dynamic Analysis For Complex Event Processing
Muhammet Oğuz
Özcan, M.S. Thesis, Defense date:
December 2015
Abstract:
Analysis facilities are developed in the course of this thesis for a domain-specific real-time and rule-based language along with a supporting tool. Such analysis facilities are required due to the need for investigating the functional correctness and stringent timing properties expected to take place in the software developed through this language. An early version of this language was developed during a Ph.D. study for the domain of fault management in mission critical systems. Five program analysis facilities are proposed and tested with randomly generated numbers of events and rules. Also, discussions about static and dynamic analysis in the event processing domain are presented along with a comparison of related existing tools. The comparisons of existing tools include the two different implementations of the similar design for interpreters for the language. The different implementations involved the languages C++ and Python.
UNIBUS: A Universal Hardware Architecture For Serial Bus Interfaces With Real-Time Support
Mehdi Duman, M.S. Thesis, Defense date: January 2015
Abstract:
Serial bus communication is widely used in different application areas such as
Ethernet in computer networking, CAN bus in in-vehicle communications, MIL-STD
1553B in military avionics and UART for peripheral device communication. This
thesis work presents UNIBUS (Universal Bus); an abstract, generic block level
hardware architecture for implementing serial bus interfaces. UNIBUS realizes
the physical and data link layer functions supporting the strict timing
requirements for bit operations and synchronization.
The hardware blocks and signal interfaces among these blocks are designed to
separate the protocol specific and protocol independent components to increase
reusability. A specific serial bus protocol can be implemented using UNIBUS by
defining the protocol specific operations and interfaces.
The versatility of UNIBUS is demonstrated by realizing CAN, UART, ARINC-708,
ARINC-717 and MIL-STD-1553B on this architecture. These serial bus interfaces
are purposely selected to be from different application areas and levels of
complexity. All these interfaces are implemented using MODELSIM simulation tool
and tested by realizing a sender and receiver that exchange messages as
specified. Furthermore MIL-STD- 1553B is fully implemented on FPGA and its
correctness is verified by communication to a commercial chip. The analysis of
the resource and power consumption of the realizations shows that the generality
of the architecture does not decrease the efficiency of the implementations.
UNIBUS decreases the hardware development time for existing and possibly new
serial bus protocols by providing the readily designed blocks and signal
interfaces. Furthermore UNIBUS increases the reliability of the design as the
reused protocol independent components that are common among different protocols
need to be verified only once and the blocks together with their interfaces are
clearly defined. UNIBUS can be both used for the development of full scale
serial bus interface components to be used in real systems as well as developing
test benches for existing products. In such deployment, a given bus interface's
desired functions can be implemented on UNIBUS to achieve a communicating
counterpart for the tested component.
Dependability Design for Distributed Real-Time Systems with Broadcast Communication
Yusuf Bora Kartal, Ph.D. Thesis, Defense date: June 2014
Abstract:
The operation of distributed systems relies on the timely exchange of message data via dependable communication networks. Previous works suggest hardware redundancy for potential faults in the underlying network infrastructure to achieve dependability. However, software faults and faults that cannot be resolved on the hardware level are not considered in the existing literature. This work proposes a new method for software fault-tolerant communication in distributed real-time systems with communication networks that support time-slotted operation and broadcast transmission.
Our method implements a dependability plane to be integrated to the existing network stack. It processes dependability information that is piggybacked on application message and uses a time synchronized checkpointing/rollback recovery strategy. The proposed dependability plane is modeled in the framework of timed input/output automata (TIOA) to formally prove its correctness and determine tight bounds for fault-recovery times. Model checking tools are employed to verify the timing and dependability properties of real-time systems. To this end, we present an algorithmic approach for converting TIOA models to be used as input of a well-known model checking software tool UPPAL. We apply our dependability plane design and integrate it to a previously developed real-time communications framework. We further verify the TIOA models of the overall protocol stack by employing our algorithmic conversion to UPPAAL.
Diagnosers for discrete event systems: improved realization and examples
Abstract:
Many complex systems in different areas such as manufacturing,
telecommunications or transportation can be modeled as Discrete Event Systems
(DES). The task of fault detection and isolation is naturally desired for every
system that has the possibility of any fault occurrences in it. To this end, a
DES machine that can detect every modeled fault after a bounded number of event
occurrence called diagnoser is used.
In this thesis, there are two diagnoser realizations corresponding to the
notions of event and language diagnosability. The proposed diagnosers function
as centralized diagnosers that run parallel to the given systems and perform
online diagnosis. Differing from similar studies, we denote our diagnosers as
improved diagnosers because they explicitly give a notification as soon as a
faulty behavior is detected. This makes our diagnosers more useful in practice.
In addition, our study simplifies the computation of the worst-case delay until
a fault is detected. Moreover, we further enhance our improved diagnoser by
applying an algorithm to remove unnecessary observations. As a result, fewer
sensors are needed and the constructed diagnosers have a smaller size. The
merits of the proposed diagnoser approach and the applicability of our
algorithmic implementation are demonstrated by a communication network system
example.
Abstract:
Discrete Event Systems (DES) are used for modeling systems such as manufacturing systems, telecommunication systems and transportation systems. It is possible to incorporate the fault model in the DES model together with a fault diagnosis approach to evaluate the robustness and the reliability of the system at the design stage. There are centralized or decentralized fault diagnosis approaches in the literature. The centralized fault diagnosis achieves stronger results however it does not scale to reasonably large systems because of its complexity. The decentralized diagnosis is applicable to real-life systems with a cost of possible misses of faults. This thesis proposes a combination of centralized and decentralized fault diagnosis for DES models. To this end, the thesis makes use of the observation that some parts of the faulty DES behavior might be detected by decentralized diagnosis while other parts need a centralized diagnoser. Hence, the overall complexity of the diagnosis is reduced while maintaining the ability to detect all faults. The thesis proposes a systematic diagnosis approach together with the algorithms and practical applications to manufacturing system and communication network examples.
The development and hardware implementation of a dynamically reconfigurable and area optimized Cyclic Redundancy Check architecture
Özcan Yurt, M.S. Thesis, Defense date: August 2013
Abstract:
The Cyclic Redundancy Check (CRC) calculation for data communication protocols is implemented by hardware calculators in several systems due to increasing throughput requirements of data communication protocols. Furthermore CRC is employed in many small scale embedded systems with different types of data communication interfaces that are implemented on FPGA. Resource utilization of these systems is frequently a critical parameter with regards to cost. In many cases, limited logic units of an FPGA have to be used very carefully to fit the design into that platform. In this thesis, we present DAROC-Dynamically Reconfigurable and ARea Optimized CRC, which is a run-time reconfigurable and area-minimized CRC calculator. The ability of reconfiguration enables DAROC calculating different CRCs for several standards with a single instance of implementation. DAROC reaches the throughput of 705 Mbps that is sufficient for the target embedded systems with less resource consumption compared to the previous reconfigurable CRC implementations.
Implementation and evaluation of the dependability plane for the Dynamic Distributed Dependable Real Time Industrial Protocol (D3RIP)
Ömer Berat Sezer, M.S. Thesis, Defense date: September 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt
Abstract:
Dynamic Distributed Dependable Real Time Ethernet Industrial Protocol (D3RIP) is a real time industrial communication protocol that runs over shared-medium Ethernet with COTS hardware. The protocol consists of an interface layer that enables time slotted communication and a coordination layer that guarantees collision avoidance and timely delivery of real time messages generated by the control application. At the current development stage, these two layers of the protocol are fully implemented and tested. The scope of this thesis is the implementation of a new plane for D3RIP to achieve dependability. To this end, mechanisms of fault detection and roll back recovery are applied. The interface of the dependability plane to the existing interface layer and coordination layer is defined. Finally the dependability plane is implemented and integrated to the existing protocol stack. A number of tests under different fault scenarios are conducted to demonstrate the plane functionality.
Implementation and evaluation of the Dynamic Distributed Real Time Industrial Protocol (D2RIP)
Adem Kaya, M.S. Thesis, Defense date: September 2013, Co-advised with Associate Prof. Dr. Klaus Werner Schmidt
Abstract:
The contemporary large-scale and complex industrial control systems such as manufacturing systems, power plants or chemical processes are realized as distributed systems. Since different controller nodes are usually physically distributed, their coordination and information exchange is commonly realized via industrial communication networks (ICNs). In the last decade, there is an ongoing research effort in both academic and industrial fields to employ Ethernet for industrial communications due to its wide acceptance and use in home and office networks. Although the conventional Ethernet technology is low-cost and very high-speed its nondeterministic behavior does not support real-time traffic.
In this thesis we present the design, implementation and evaluation of the novel ICN protocol D²RIP (Dynamic Distributed Real-time Industrial Communication Protocol) that was proposed in previous work. D²RIP is a fully distributed protocol over shared-medium Ethernet with COTS (Commercial Off-The-Shelf) hardware and provides real-time message delivery guarantees, supports non-real-time traffic. As a distinctive feature in comparison to other ICNs over Ethernet that only support static allocation of real-time and non-real-time bandwidth, D²RIP allows for dynamic allocation of the network capacity among the participating nodes by exploiting knowledge about the deterministic system behavior of industrial systems.
QoC and QoS bargaining for message scheduling in
networked control systems
Sinan Senol, Ph.D. Thesis, Defense date: June 2012, Co-advised with Prof. Dr. Kemal Leblebicioğlu
Abstract:
Networked Control Systems (NCS) are distributed control systems where the sensor signals to the controllers and the control data to the actuators are enclosed in messages and sent over a communication network. On the one hand, the design of an NCS requires ensuring the stability of the control system and achieving system response that is as close as possible to that of an ideal system which demands network resources. On the other hand, these resources are limited and have to be allocated efficiently to accommodate for future system extensions as well as applications other than control purpose. Furthermore the NCS design parameters for the control system messages and the message transmission over the network are interdependent. In this thesis, we propose “Integrated NCS Design (INtERCEDE: Integrated NEtwoRked Control systEm DEsign)” a novel algorithmic approach for the design of NCS which ensures the stability of the control system, brings system response to that of an ideal system as close as desired and conserves network bandwidth at the same time. The core of INtERCEDE is a bargaining game approach which iteratively calculates the message parameters and network service parameters. Our experimental results demonstrate the operation of INtERCEDE and how it computes the optimal design parameters for the example NCS.
Simulation And Performance Evaluation Of A Distributed Real-Time Communication Protocol For Industrial Embedded Systems
Güray Aybar, M.S. Thesis, Defense date: December 2011
Abstract:
The
Dynamic Distributed Dependable Real-Time Industrial communication Protocol (D3RIP)
provides service guarantees for Real-Time traffic and integrates the dynamically
changing requirements of automation applications in their operation to
efficiently utilize the resources. The protocol dynamically allocates the
network resources according to the respective system state. To this end, the
protocol architecture consists of an Interface
Layer that provides time-slotted operation and a Coordination Layer that assigns each time slot to a unique
transmitter device based on a distributed computation.
In
this thesis, a software simulator for D3RIP is developed. Using the D3RIP
Simulator, modifications in D3RIP can be easily examined without
facing complexities in real implementations and extensive effort in terms of
time and cost. The simulator simulates the Interface Layer, the Coordination
Layer and additionally, the Shared Medium.
Hence, using the simulator, the system-protocol couple can be easily analyzed,
tested and further improvements on D3RIP can be achieved with the
least amount of effort.
The
simulator implements the Timed Input Output Automata (TIOA) models of the D3RIP
stack components using C++. The resulting code is compiled on GCC (Gnu Compiler
Collection). The logs of the simulation runs and the real system with 2 devices
connected via cross 100MbE cables are compared. In a 3ms time slot, the
simulator and the system incidents differ about 135µs on the average, causing no asynchronousity in
their instantaneous operational states. The D3RIP simulator is useful in keeping
track of any variable in the D3RIP system automaton at any instant up
to 1µs
resolution.
Implementation and Evaluation of a Synchronous Time-Slotted Medium Access Protocol for Networked Industrial Embedded Systems
Ahmet Korhan Gözcü, M.S. Thesis, Defense date: September 2011
Abstract:
Dynamic Distributed Dependable Real-time Industrial communication Protocol family (D3RIP), has been proposed in the literature considering the periodic or event-based traffic characteristics of the industrial communication networks. D3RIP framework consists of two protocol families: Interface Layer (IL) protocol family, which is responsible for providing the accurate time-division multiple access (TDMA) on top of a shared-medium broadcast channel, and Coordination Layer (CL), which is defined to fulfill the external requirements of IL. In this thesis, the hardware adaptations of the two protocols, Real-time Access Interface Layer (RAIL) and Time-slotted Interface Layer (TSIL), of the IL protocol family, are implemented. Their performance on both personal computers (PC) and development kits (DK) are observed.
Implementing and Evaluating the Coordination Layer and
Time-Synchronization of a New Protocol for Industrial Communication Networks
Ulaş Turan, M.S. Thesis, Defense date: September 2011
Abstract:
Currently automation components of large-scale industrial systems are realized with distributed controller devices that use local sensor/actuator events and exchange shared events with communication networks. Fast paced improvement of Ethernet provoked its usage in industrial communication networks. The incompatibility of standard Ethernet protocol with the real-time requirements encouraged industry and academic researchers to provide a resolution for this problem. However, the existing solutions in the literature suggest a static bandwidth allocation for each controller device which usually leads to an inefficient bandwidth use.Dynamic Distributed Dependable Real-time Industrial Communication Protocol (D3RIP) family dynamically updates the necessary bandwidth allocation according to the messages generated by the control application. D3RIP is composed of two protocols; interface layer that provides time-slotted access to the shared medium based on an accurate clock synchronization of the distributed controller devices and coordination layer that decides the ownership of real-time slots. In this thesis, coordination layer protocol of D3RIP family and the IEEE 1588 time synchronization protocol is implemented and tested on the real hardware system that resembles a factory plant floor. In the end, we constructed a system that runs an instance of D3RIP family with 3ms time-slots that guarantees 6.6ms latency for the real-time packets of control application. The results proved that our implementation may be used in distributed controller realizations and encouraged us to further improve the timing constraints.
Ethernet Based Real Time Communications for Embedded Systems
Ozan Yılmaz, M.S. Thesis, Defense date: May 2010
Abstract:
Fast paced improvement of Ethernet technology has also received attention in the industry field like it did in other fields and ways of usage have started to be studied. As it is understood that the standard Ethernet protocols cannot be used due to the unsatisfied real time requirements, industrial and academic researchers have started to develop solutions to overcome this deficiency. In this thesis, the real hardware adaptations of Real Time Ethernet and RTXX protocol algorithms are implemented and their behaviors on the hardware are observed. Each parameter that affects the system’s real time behavior is individually examined and the solution proposals are discussed.
Testing distributed real-time systems with a distributed test approach
Gokhan Oztas, M.S. Thesis, Defense date: May 2008
Abstract:
Software testing is an important phase the of software development cycle which reveals faults and ensures correctness of the developed software. Distributed realtime systems are mostly safety critical systems for which the correctness and quality of the software is much more significant. However, majority of the current testing techniques have been developed for sequential (non real-time) software and there is a limited amount of research on testing distributed real-time systems. In this thesis, a proposed approach in the academic literature "testing distributed real-time systems using a distributed test architecture" is implemented and compared to existing software testing practices in a software development company on a case study. Evaluation of the results show the benefits of using the considered distributed test approach on distributed real-time systems in terms of software correctness.
An evaluation of aspect-oriented programming for embedded real-time systems
Yusuf Bora Kartal, M.S. Thesis, Defense date:
Abstract:
In this thesis work, a detailed evaluation of the use of Aspect Oriented Programming for the implementation of crosscutting concerns in embedded real-time systems is presented. The implementations are first tested in terms of software quality attributes. Then a detailed analysis of the two implementations, according to embedded real-time performance metrics has been carried out. Evaluation results show the benefits of Aspect Oriented Programming in embedded real-time systems.