Student VLSI Design Contest

Contest Entry Requirements

The purpose of this contest is to promote excellence in education for integrated circuit designers at universities. It provides competition between students participating in classes and in research who design and fabricate integrated circuits.

The contest will be split into two groups, a "novice" class and an "experienced" class. The novice class is intended for students who are taking an introductory quarter/semester class in which they design an integrated circuit. The experienced class is intended for students who have already completed the introductory class and are continuing in an advanced course or doing research that involves the design and fabrication of integrated circuits. Entries are typically due in early May, and final judging will take place 2-3 weeks later.

Both contests will be for the most innovative VLSI project created by a student or team of students who are or have been enrolled in VLSI classes at any of the participating schools. A panel of judges from industry, representing the companies that donate prize money, will evaluate the entries and decide how the money will be divided.

CRITERIA FOR ENTERING THE CONTEST

The contest is for any full time graduate or undergraduate student at any of the participating universities. Students are eligible to enter, provided they had not, before the completion of their projects, been employed as integrated circuit designers in industry or in full-time VLSI design positions at their respective universities.

To be eligible for the contest, a chip must meet functional needs and be non-proprietary. It is desirable but not mandatory that the chips be fabricated and tested. If your chip is tested, you must report the results even if they were negative. A testing procedure should be included whether or not you have tested the chips.

All work on the project must be done using facilities, equipment and design tools provided by the respective university. Any design style supported at the university may be used, including full-custom, standard-cell, symbolic, compiled, FPGAs, etc.

REPORT SPECIFICATIONS AND HINTS

Judging will be based upon the written report, which must conform to the outline described herein. Each report shall be a total of no more than 8 pages for the novice class and 12 pages for the experienced class including title page, abstract, text, figures, references, etc.; no pages beyond this will be accepted. Text should be 10 pt and double spaced. The pages must all be 8.5 x 11 inches, except one (optional) for a layout which may fold out as large as a C size sheet. The report should be stapled in the upper left corner and have no cover of any kind. Each paper is expected to follow the form specified below, including all items appropriate for the specific project.

Since projects are judged solely upon the written reports, clarity and completeness of the report are of paramount importance. Spelling and grammatical errors will not be impressive. Writing style should be clear and concise. Remember that the judges' expertise may not be in the area of your project. Make your explanations straightforward and understandable.

Design for testability is an important issue. Discuss testing issues you have considered in the design and approaches you took or will take in testing. Engineering specifications and performance statistics can be efficiently presented in tabular form.

REPORT OUTLINE

1. Title Page (a page by itself).

2. Abstract (no more than a 1/2 page, on a page by itself).

3. System Overview. Include motivation for designing the chip. Is VLSI appropriate? Does this design satisfy the system requirements? What is unique about this project? What novel ideas or elegant solutions does the design include?

4. Implementation and engineering considerations (bulk of the report):

Specifications: functional, timing, electrical, and environmental (temperature).
Tradeoffs: architectural and circuit tradeoffs, I/O considerations, floor-planning and interconnect approaches. Emphasis should be placed on why you did what you did.
Timing and Critical Paths. What clocking scheme is used? Why? Which paths are critical? Have you simulated or measured their delays?
Block Diagram, Logic / Circuit Diagrams, and Algorithms.
Final Layout Plot (annotate so various blocks can be identified).
Verification and Simulation (keep it brief): how did you assure that the chip would work as specified?
Testing: how did you, or will you, test this part with I/O pins only? What test equipment did you use? Actual test results, if available, should be summarized.
Chip statistics: die size, total power, number of transistors, density of layout, maximum clock speed, etc.

5. Summary

6. References

JUDGING CRITERIA

Entries will be judged on the following criteria, with weights as shown:

1. 50% - Soundness of engineering, including evaluation of tradeoffs and ingenuity at all levels of design activity (note that ingenuity is usually seen in simplicity, rather than added complexity).

2. 30% - Clarity of the functional specification, system description, and chip description.