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CHARM Research Group
Computer Hardware & Acceleration • Resource-Optimized • Model-Driven

About

CHARM (Computer Hardware and Acceleration for Resource-Optimized, Model-Driven Systems) is a research group focused on performance-oriented system design across compute, network, and storage domains. Our work spans reconfigurable and fixed-function architectures, high-throughput hardware acceleration, and optimization techniques for modern cloud and datacenter platforms. We emphasize resource-aware design, applying analytical and machine-learning-based models to guide architectural decisions, task scheduling, and system-level tradeoffs. A core theme is programmable dataplane networking, including packet processing, switching, and SmartNIC/FPGA/GPU-based network functions. CHARM integrates low-level design with high-level modeling to enable scalable, predictable, and energy-efficient computing infrastructure for data-intensive applications.

Contact

Email: charm@metu.edu.tr
Address: Department of Electrical and Electronics Engineering, Middle East Technical University (METU), Ankara, Türkiye

People

Publications

International Journal

  1. F. Koltuk and E. Güran Schmidt, “Uniformity and Independence of H3 Hash Functions for Bloom Filters,” IEEE Transactions on Computers, vol. 73, no. 8, pp. 1913–1923, Aug. 2024.
  2. S. Zengin and E. G. Schmidt, “A Fast and Accurate Hardware String Matching Module with Bloom Filters,” IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 2, pp. 305–317, Feb. 1 2017.
  3. N. Ayyildiz, E. G. Schmidt and H. C. Guran, “S-DIRECT: Scalable and Dynamically Reconfigurable TCAM Architecture for High-speed IP Lookup,” The Computer Journal, vol. 58, no. 6, pp. 1443–1455, 2015.
  4. M. Sanli, E. G. Schmidt and H. C. Guran, “Hardware Design and Implementation of Packet Fair Queuing Algorithms for the Quality of Service Support in the High-speed Internet,” Elsevier Computer Networks, vol. 56, no. 13, pp. 3065–3075, 2012.
  5. M. Sanli, E. G. Schmidt and H. C. Guran, “FPGEN: A Fast, Scalable and Programmable Traffic Generator for the Performance Evaluation of High-speed Computer Networks,” Elsevier Performance Evaluation, vol. 68, no. 12, pp. 1276–1290, 2011.
  6. M. Soysal and E. G. Schmidt, “Machine Learning Algorithms for Accurate Flow-based Network Traffic Classification: Evaluation and Comparison,” Elsevier Performance Evaluation, vol. 67, no. 6, pp. 451–467, 2010.
  7. S. Ece (Guran) Schmidt and Hyong S. Kim, “A new scalable service discipline for real-time traffic: The framed-deadline scheduler,” Elsevier Computer Communications, vol. 30, no. 6, pp. 1258–1277, 2007.
  8. S. Ece (Guran) Schmidt and Hyong S. Kim, “Frame-counter scheduler: A novel QoS scheduler for real-time traffic,” Elsevier Computer Communications, vol. 29, no. 12, pp. 2181–2200, 2006.

International Conference

  1. F. Yazıcı, A. S. Yıldız, A. Yazar, E. G. Schmidt, “A Novel Scalable On-chip Switch Architecture with Quality of Service Support for Hardware Accelerated Cloud Data Centers,” IEEE International Conference on Cloud Networking, 2020.
  2. C. Canpolat and E. G. Schmidt, “Dynamic User Count Aware Resource Allocation for Network Slicing in Virtualized Radio Access Networks,” 2020 25th IEEE Symposium on Computers and Communications (ISCC), Rennes, France, 2020.
  3. F. Koltuk and E. G. Schmidt, “A Novel Method for the Synthetic Generation of Non-I.I.D Workloads for Cloud Data Centers,” 2020 25th IEEE Symposium on Computers and Communications (ISCC), Rennes, France, 2020.
  4. N. U. Ekici, K. W. Schmidt, A. Yazar and E. G. Schmidt, “Resource Allocation for Minimized Power Consumption in Hardware Accelerated Clouds,” 2019 28th International Conference on Computer Communication and Networks (ICCCN), Valencia, Spain, 2019.
  5. A. Erol, A. Yazar and E. G. Schmidt, “OpenStack Generalization for Hardware Accelerated Clouds,” 2019 28th International Conference on Computer Communication and Networks (ICCCN), Valencia, Spain, 2019.
  6. M. Sanli, A. Pehlivanli, and E. G. Schmidt, “Window Based Fair Aggregator for the Scalable Support of QoS Guarantees in the Backbone: An Experimental Performance Study,” IEEE ICNC, 2016.
  7. M. Sanli, E. G. Schmidt and H. C. Guran, “A Flow Aggregation Method for the Scalable and Efficient Quality of Service Support in Next Generation Networks,” IEEE GLOBECOM, 2013.

Recent SIU Papers

  1. Doğan, Onat Deniz, et al. “I²CLOUDMAN: DQN-Enhanced ILP Model for Optimal Virtual Machine Placement and Migration in Cloud Data Centers.” 2025 33rd SIU. IEEE, 2025.
  2. U. Doğan, A. Koyun, S. S. Yalçın and E. Güran Schmidt, “RISC-V Simulator Library for Real-time Applications: Development and Verification,” 2024 32nd SIU. IEEE, 2024.
  3. E. B. Yitim and E. Güran Schmidt, “An AXI Data Shaper for Heterogeneous FPGA System-on-Chip (SoC) Architectures,” 2022 30th SIU. IEEE, 2022.
  4. A. Tırlıoğlu, Ö. B. Demir, A. Yazar, E. G. Schmidt, “Bulut Bilişim için Donanım Hızlandırıcılar: Özellikler ve Gerçekleştirim,” 2021 29th SIU. IEEE, 2021.
  5. F. Yazıcı, A. S. Yıldız, A. Yazar, E. G. Schmidt, “Donanım Hızlandırıcılı Bulut Bilişim Sistemleri için Yonga-üstü Anahtar Mimarisi,” 2020 28th SIU. IEEE, 2020.
  6. F. Koltuk, E. G. Schmidt, “Bulut Veri Merkezleri için Gerçekçi İş Yükü Üretimi,” 2020 28th SIU. IEEE, 2020.
  7. A. Erol, A. Yazar, E. G. Schmidt, “Heterojen Bulut Kaynaklarının Yönetimi İçin OpenStack Genelleştirimi,” 2019 27th SIU. IEEE, 2019.
  8. F. Koltuk, A. Yazar, E. G. Schmidt, “CLOUDGEN: Bulut Bilişim Sistemlerinin Başarım Değerlendirmesi için İş Yükü Üretimi,” 2019 27th SIU. IEEE, 2019.
  9. N. U. Ekici, K. W. Schmidt, A. Yazar, E. G. Schmidt, “ACCLOUD-MAN — Power Efficient Resource Allocation for Heterogeneous Clouds,” 2019 27th SIU. IEEE, 2019.
  10. A. Yazar, A. Erol, E. G. Schmidt, “ACCLOUD: FPGA ile Hızlandırılmış Yeni bir Bulut Mimarisi,” 2018 26th SIU. IEEE, 2018.
  11. G. Eral, E. G. Schmidt, “FASST: Yazılım Tanımlı Bilgisayar Ağları için Yüksek Başarımlı, Ölçeklenebilir bir Kural Tablosu Donanım Mimarisi,” 2018 26th SIU. IEEE, 2018.

Projects

In Progress

  1. Industrial Research Project conducted with Aselsan Inc. and METU TTO: “High-speed (40G-100G) Packet Processing”, Principal Investigator, Project end date: May 2027.
  2. Industrial Research Project conducted with BullTech and METU TTO: “Risk Management for FPGA-Based High Frequency Trading Users”, Principal Investigator, Project end date: December 2026.

Completed

  1. Industrial Research Project conducted with BullTech and OTEST: “Development of a New FPGA-based UPF Device Architecture for 5G Networks”, Principal Investigator, Project end date: April 2024.
  2. Industrial Research Project conducted with SAGE and OTEST: “ozgur: A Custom RISC-V Processor Core and Hardware Accelarator Platform for Real-time Embedded Applications,” Principal Investigator, Project end date: July 2024.
  3. TUBITAK (The Scientific and Technological Research Council of Türkiye) 1003 Priority Areas Research Project - ACCLOUD (ACCELERATED CLOUD): A Novel, FPGA-Accelerated Cloud Architecture – FPGA İle Hızlandırılmış Yeni Bir Bulut Mimarisi, Principal Investigator (2018-2021)
    Project Abstract
    ACCLOUD Web Page
    Hardware Accelerated Cloud Computing Lecture
  4. METU Research Project: “METU-STARS: Yüksek Başarımlı Yeni Bir Sistematik Yazılım Tanımlı Ağ (Software Defined Network-SDN) Yönetimi – A Novel and High-performance Systematic Software Defined Network-SDN Management Method”, Principal Investigator, Project end date: May 2019.
  5. METU Research Project: “METU-HAS: Yüksek Başarımlı Yeni Bir Sistematik HTTP Adaptive Streaming (HAS) Yöntemi – METU-HAS: A Novel and High-performance Systematic HTTP Adaptive Streaming (HAS) Method”, Principal Investigator, Project end date: December 2017.
  6. METU Research Project: “Bilgisayar ağları üzerinde gerçek zamanlı trafik iletimi için kullanılan zamanlama algoritmaları analizi – Analysis of scheduling algorithms for real-time communication over computer networks”, Principal Investigator, Project end date: December 2005.
  7. Industrial project grant from Pittsburgh Digital Greenhouse: “Network switch on a single chip”, Researcher, Project end date: 2002.

Theses

Ph.D.

  1. Fast, Efficient and Dynamically Optimized Data and Hardware Architectures for String Matching, Salih Zengin, Ph.D. Thesis, Defense date: September 2014, Co-advised with Prof. Dr. Hasan Guran.
  2. Design and implementation of Hardware Architectures for High-speed IP Address Lookup, Nizam Ayyıldız, Ph.D. Thesis, Defense date: August 2013, Co-advised with Prof. Dr. Hasan Guran.
  3. Design and implementation of scheduling and switching architectures for high-speed networks, Mustafa Sanlı, Ph.D. Thesis, Defense date: October 2011, Co-advised with Prof. Dr. Hasan Guran.

M.Sc.

  1. Dynamic, Adaptive, And Optimal Resource Allocation And Migration In Cloud Data Centers, Onat Deniz Doğan, M.Sc. Thesis, Defense date: July 2025, Co-advised with Prof. Dr. Klaus Werner Schmidt.
  2. An FPGA-Accelerated String-Matching Engine, Süleyman Samet Yalçın, M.Sc. Thesis, Defense date: November 2024.
  3. Cycle-Accurate Functional Simulation of RISC-V Processors for Embedded Applications: Timing Model Construction, Validation and Performance Evaluation, Utkucan Doğan, M.Sc. Thesis, Defense date: August 2024.
  4. Hardware Accelerators for High Throughput Packet Classification in Computer Networks, Doğu Erkan Arkadaş, M.Sc. Thesis, Defense date: August 2024.
  5. Hardware Accelerated Packet Parsers and Deparsers for High-Throughput Flow Classification in Computer Networks: Design, Implementation and Evaluation, Ömer Bayram Demir, M.Sc. Thesis, Defense date: August 2024.
  6. High-Throughput Bloom Filter Design: Systematic Parameter Selection and FPGA Implementation, Efe Berkay Yitim, M.Sc. Thesis, Defense date: July 2024.
  7. Optimal Resource Allocation and Migration Decision for Virtual Machine Requests in Cloud Data Centers, Nazım Kerem Mert, M.Sc. Thesis, Defense date: August 2023, Co-advised with Prof. Dr. Klaus Werner Schmidt.
  8. A Novel and Precise False Positive Probability Computation for Bloom Filters Implemented with Universal Hash Functions, Furkan Koltuk, M.Sc. Thesis, Defense date: August 2022.
  9. Extension of an Open Source Resource Management Tool For Heterogeneous Cloud Data Centers: Implementation And Evaluation, Taha Doğan, M.Sc. Thesis, Defense date: February 2022.
  10. A Workflow for Offering Hardware Accelerators as a Cloud Computing Service: Implementation and Evaluation, Anıl Tırlıoğlu, M.Sc. Thesis, Defense date: February 2022.
  11. Design, Implementation And Verification Of A High-Speed On-Chip Packet Switch, Ayhan Sefa Yıldız, M.Sc. Thesis, Defense date: February 2022.
  12. A Novel Flexible On-chip Switch Architecture for Reconfigurable Hardware Accelerators, Fatih Yazıcı, M.Sc. Thesis, Defense date: August 2021.
  13. Optimal Dynamic Resource Allocation for Heterogeneous Cloud Data Centers, Nazım Umut Ekici, M.Sc. Thesis, Defense date: September 2019.
  14. Generalized Resource Management for Heterogeneous Cloud Data Centers, Ahmet Erol, M.Sc. Thesis, Defense date: September 2019.
  15. A Low Latency, High Throughput and Scalable Hardware Architecture for Flow Tables in Software Defined Networks, Göksan Eral, M.Sc. Thesis, Defense date: September 2016.
  16. Implementation and Performance Analysis Of Switch Fabric Schedulers With a New Accurate Simulator Software, Ahmet Ada, M.Sc. Thesis, Defense date: September 2014.
  17. Switch Fabric Schedulers with Intelligent Multi-Class Support: Design, Implementation and Evaluation on FPGA, Murat Akpınar, M.Sc. Thesis, Defense date: September 2014.
  18. The development and hardware implementation of a dynamically reconfigurable and area optimized Cyclic Redundancy Check architecture, Özcan Yurt, M.Sc. Thesis, Defense date: August 2013.
  19. The development and hardware implementation of a high-speed adaptable packet switch fabric, Erdem Eyüp Akbaba, M.Sc. Thesis, Defense date: January 2013.
  20. Routing algorithms for on-chip networks, Maksat Atagoziyev, M.Sc. Thesis, Defense date: December 2007.

Work in Progress

  1. Hardware-accelerated packet processing
  2. Hardware-accelerated ML-based prediction for ultra low latency applications
  3. On-chip switch architectures for accelerator pipelines
  4. ML and ILP hybrid techniques for optimal cloud resource allocation

Announcements